1. Field of the Invention
Embodiments of the present invention generally relate to semiconductor devices and methods of fabricating the same, and in particular, to a method of fabricating an ultra-shallow junction in Field Effect Transistor (FET) devices.
2. Description of the Related Art
Ultra-large-scale integrated (ULSI) circuits typically include more than one million transistors that are formed on a semiconductor substrate and which cooperate to perform various functions within an electronic device. Such transistors may include complementary metal-oxide-semiconductor (CMOS) field effect transistors and metal oxide semiconductor field effect transistors (MOSFET).
A CMOS transistor includes a gate structure that is disposed between a source region and a drain region defined in the semiconductor substrate. The gate structure generally comprises a gate electrode formed on a gate dielectric material. The gate electrode controls a flow of charge carriers, beneath the gate dielectric, in a channel region that is formed between the drain region and the source region, so as to turn the transistor on or off. The channel, drain, and source regions are collectively referred to in the art as a “transistor junction”. There is a constant trend to reduce dimensions of the transistor junction in order to facilitate an increase in the operational speed of such transistors.
The gate electrode is generally formed of doped polysilicon (Si) while the gate dielectric material may comprise a thin layer (e.g., <20 Å) of a high dielectric constant material (e.g., a dielectric constant greater than 4.0) such as silicon dioxide (SiO2) or N-doped silicon dioxide, and the like.
The CMOS transistor may be fabricated by defining source and drain regions in the semiconductor substrate using an ion implantation process. However, smaller dimensions for the transistor junctions have necessitated the formation of source and drain regions with reduced depths (e.g., depths of between 100 to 500 Å). Such ultra shallow junctions require abrupt interfaces that are difficult to form using ion implantation techniques due to ion-channeling and transient enhanced diffusion phenomena (TED). Dopants experience greatly enhanced diffusion or TED during post-implant annealing due to interaction of the dopants with excess silicon interstitials. This enhanced diffusion results in a deeper source/drain junction and poorer junction profile.
Several methods have attempted to reduce TED during formation of ultra shallow junctions. One method for fabricating the ultra shallow transistor junctions is called carbon co-implantation in which carbon is co-implanted with a dopant such as boron. Although carbon co-implantation is successful in reducing TED, carbon co-implantation suffers from the disadvantage of creating a high number of point defects in the film.
Another method uses fluorine co-implants to reduce TED during annealing. However, this method suffers from the same disadvantages as carbon co-implantation, i.e. point defects remain after annealing.
Therefore, there is a need for an improved method for fabricating an ultra shallow junction of a field effect transistor.